module: sense_instability_ds
description: 
timing_sensitivity:  posedge clk
parameters:  
inputs:  bool in, bool clk, bool enable
outputs:  bool assert
classes:  
static_variables:  int rep_count, int same_val_count,
                   int prev_in
init:  
rep_count = 0;
same_val_count = 0;
prev_in = 0;

end:  
code:  

if (enable == 1)
   {
   if (in == prev_in)
      same_val_count++;
   else
     {
      if (assert == 0)
         {
          if (same_val_count >= 15)
             rep_count++;
          else
             rep_count = 0;
         }
      else
         {
          if (same_val_count < 15)
             rep_count++;
          else
             rep_count = 0;
         }
      if (rep_count >= 6)
         {
          assert = (assert == 0) ? 1 : 0;
          rep_count = 0;
         }
      same_val_count = 0;
     }
   }
else
   assert = 0;

prev_in = in;
