module: dac_bits2double
timing_sensitivity: posedge clk
description: 
parameters:  int num_active_bits, double mismatch_stddev
inputs:  bool clk, bool in[29:0]
outputs:  double out
classes:  Vector mismatch_vec(), Vector out_vec()
static_variables: int input_range;
init:  
if (num_active_bits < 2)
  {
   printf("error in 'dac_bits2double':\n");
   printf("  'num_active_bits' must be greater than one\n");
   printf("  in this case, 'num_active_bits' was set to '%d'\n",
             num_active_bits);
   printf("  -> please change these parameters in your schematic\n");
   exit(1);
  }
if (num_active_bits > 30)
  {
   printf("error in 'dac_bits2double':\n");
   printf("  'num_active_bits' must be less than 31\n");
   printf("  in this case, 'num_active_bits' was set to '%d'\n",
             num_active_bits);
   printf("  -> please change these parameters in your schematic\n");
   exit(1);
  }

input_range = (int) floor(pow(2.0,(double) num_active_bits) + 0.5);
gauss_ran_vector(mismatch_stddev, input_range, mismatch_vec);
out_vec.set_length(input_range);
out = 0.0;

code:  
// this code only executes on rising edges of clk due to
// timing_sensitivity: statement above

int input_value;
double quant_value;

input_value = in.get_decimal_value();
quant_value = ((double) input_value) + mismatch_vec.get_elem(input_value);

out = quant_value/((double) input_range);
