***** Hspice Netlist for Cell 'dfe_simple' *****

************** Module add2 **************
.subckt add2 in1 in2 out
.ends add2

************** Module constant **************
.subckt constant out consval=1
.ends constant

************** Module edgemeasure **************
.subckt edgemeasure in out
.ends edgemeasure

************** Module gain **************
.subckt gain a y gain=1
.ends gain

************** Module inv **************
.subckt inv a y
.ends inv

************** Module limitamp **************
.subckt limitamp in out
.ends limitamp

************** Module mux2 **************
.subckt mux2 in0 in1 y sel
.ends mux2

************** Module rcfilter **************
.subckt rcfilter in out fo=1
.ends rcfilter

************** Module signal_source **************
.subckt signal_source phase out clk stype=0 freq=1
.ends signal_source

************** Module sub2 **************
.subckt sub2 in1 in2 out
.ends sub2

************** Module trline_load2 **************
.subckt trline_load2 eil out erl zol=1 zor=1 c1=1 sim_order=1 c2=1 l=1
.ends trline_load2

************** Module trline_section **************
.subckt trline_section eil err erl erl_p eir delay=1 gain=1 sim_order=1
.ends trline_section

************** Module vco **************
.subckt vco vctrl squareout sineout freq=1 kvco=1
.ends vco

************** Module xor2 **************
.subckt xor2 a b y
.ends xor2

************** Module fixed_delay **************
.subckt fixed_delay in out delay=100e-12
.ends fixed_delay

************** Module link_channel **************
.subckt link_channel channel_in channel_out
.ends link_channel

************** Module nonlin_amp **************
.subckt nonlin_amp in out a0=0 a1=1 a2=0 a3=0 min=-1 max=1
.ends nonlin_amp

************** Module regen_latch **************
.subckt regen_latch d clk q gain=1 f_bw=10e9
.ends regen_latch

************** Module trline_source_impedance **************
.subckt trline_source_impedance in out outr_p outr zo=50 zor=50 amp=1.0 offset=0 sim_order=0
.ends trline_source_impedance

************** Module trline_sub **************
.subckt trline_sub in1 out in2 sim_order=0
xi0 in1 in2 out sub2
.ends trline_sub

************** Module jitter_edgemeasure **************
.subckt jitter_edgemeasure in out
xi0 in n0 limitamp
xi1 n0 out edgemeasure
.ends jitter_edgemeasure

************** Module regen_flipflop **************
.subckt regen_flipflop clk d q gain=1.0 f_bw=10e9
xi2 clk n0 inv
xi0 d n0 n1 regen_latch gain=gain f_bw=f_bw
xi1 n1 clk q regen_latch gain=gain f_bw=f_bw
.ends regen_flipflop

************** Module channel_model **************
.subckt channel_model in out inb k=1.0 fp1=1e9 fp2=1e9 fp3=1e9
xi2 n2 n0 rcfilter fo=fp1
xi0 n0 n1 rcfilter fo=fp2
xi1 n1 n6 rcfilter fo=fp3
xi3 in n2 gain gain=k
xi4 n5 n3 rcfilter fo=fp1
xi5 n3 n4 rcfilter fo=fp2
xi6 n4 n7 rcfilter fo=fp3
xi7 inb n5 gain gain=k
xi8 n6 n7 out sub2
.ends channel_model

************** Module differential_to_digital **************
.subckt differential_to_digital in out
xi0 in n1 n0 add2
xi1 n0 out gain gain=0.5
xi2 n1 constant consval=1
.ends differential_to_digital

************** Module analog_summer **************
.subckt analog_summer in out h1 h2 h3 h4 h5 a0=0 a1=1 a2=0 a3=0 h1=1 h2=1 h3=1 bw=10e9 h4=1 h5=1
xi3 n1 out rcfilter fo=bw
xi4 in n0 nonlin_amp a0=a0 a1=a1 a2=a2 a3=a3
xi0 n0 n9 n10 sub2
xi1 n10 n7 n8 sub2
xi2 n8 n5 n6 sub2
xi8 n6 n3 n4 sub2
xi9 n4 n2 n1 sub2
xi5 h1 n9 gain gain=h1*a1*0.5
xi6 h2 n7 gain gain=h2*a1*0.5
xi10 h4 n3 gain gain=h4*a1*0.5
xi7 h3 n5 gain gain=h3*a1*0.5
xi11 h5 n2 gain gain=h5*a1*0.5
.ends analog_summer

************** Module channel_model_trline **************
.subckt channel_model_trline out in inb amplitude=1 delay=100e-12 offset=0 zo=50 zs=50 zl=50 c1=1e-12 c2=1e-12 l=1e-12 loss=1
xi2 in n2 n0 n1 trline_source_impedance zo=zs zor=zo amp=amplitude offset=offset
xi4 inb n8 n6 n7 trline_source_impedance zo=zs zor=zo amp=amplitude offset=offset sim_order=1
xi1 n2 n3 n1 n0 n4 trline_section delay=delay gain=loss sim_order=2
xi3 n8 n9 n7 n6 n10 trline_section delay=delay gain=loss sim_order=3
xi0 n3 n5 n4 trline_load2 zol=zo zor=zl c1=c1 sim_order=4 c2=c2 l=l
xi5 n9 n11 n10 trline_load2 zol=zo zor=zl c1=c1 sim_order=5 c2=c2 l=l
xi6 n5 out n11 trline_sub sim_order=6
.ends channel_model_trline

************** Module tap_calibration **************
.subckt tap_calibration clk_out out outb out_diff tsym=100e-12 clk_delay=100e-12 amplitude=1 sel=0
xi1 n0 constant consval=0
xi4 n0 n1 n8 vco freq=1/tsym kvco=1
xi2 edge2 edge1 fixed_delay delay=tsym
xi3 edge1 edge2 n3 xor2
xi0 n0 edge2 n9 vco freq=1/(1e3*tsym) kvco=1
xi7 n1 clk_out fixed_delay delay=clk_delay
xi6 n3 n2 out_diff n4 mux2
xi8 n5 out gain gain=amplitude
xi5 n0 n2 n10 signal_source stype=3 freq=1/tsym
xi12 n4 constant consval=sel
xi13 out_diff n5 differential_to_digital
xi14 n6 outb gain gain=amplitude
xi15 n7 n6 differential_to_digital
xi16 out_diff n7 gain gain=-1
.ends tap_calibration

************** Module dfe_simple **************
.subckt dfe_simple example_param=1.0
xi5 n1 n5 n2 channel_model fp2=5e9 fp3=10e9
xi0 clk sum_out out_pb1 regen_flipflop
xi2 clk out_pb1 out_pb2 regen_flipflop
xi3 clk out_pb2 out_pb3 regen_flipflop
xi4 clk out_pb3 out_pb4 regen_flipflop
xi8 clk out_pb4 out_pb5 regen_flipflop
xi7 sum_out edge_out jitter_edgemeasure
xi9 n0 edge_ref jitter_edgemeasure
xi1 in sum_out out_pb1 out_pb2 out_pb3 out_pb4 out_pb5 analog_summer h1=0.495 h2=0.268 h3=0.143 h4=0.076 h5=0.037
xi10 n6 n1 n2 channel_model_trline c1=2e-12 c2=2e-12 l=1e-9
xi6 clk n1 n2 n0 tap_calibration clk_delay=50e-12 sel=1
xi11 n1 n4 link_channel
xi12 n2 n3 link_channel
xi13 n3 n4 in sub2
.ends dfe_simple


.end

